(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method to monitor radiation induced charging effect during the creation of semiconductor devices.
(2) Description of the Prior Art
During the creation of semiconductor devices, layers of semiconductor material are patterned and shaped to form separate elements of the devices. This patterning and shaping of the layers of semiconductor material typically requires the radiation of these layers by sources of high energy, whereby the energy that is imparted to the exposed layer determines the change that is affected in the exposed layer. Examples of such radiation are impurity implants that are performed in for instance the surface of a substrate in order to created regions of different conductivity in the exposed regions of the substrate. Well-known device features such as p-well and n-well impurities and the creation of Field Effect Transistor related source/drain implants fall into this category of impurity implants. Another example is the frequently applied processing step of plasma etching, whereby a top layer of a layer of semiconductor material, such as the surface of a silicon substrate, is selectively removed by a high-energy plasma that controllably erodes and therewith removes the upper layer of the layer of semiconductor material.
A key component of these methods of exposure is the use of electrical charges, of various compositions and densities and energy content, that are used for various objectives of which two have been highlighted above. As a side effect of the controlled process, electrical charges can be expected to accumulate in non-conductive or semi-conductive elements of the device that is being created. These electrical charges can be trapped between for instance layers of insulating material. Continued accumulation of the electrical charges may result in creating an electromagnetic field in the region that is being charged of a magnitude large enough that molecular and structural damage may result in the accumulating layer.
It is therefore required, in order to avoid damage to elements that form part of a semiconductor device, that the accumulated electrical charges are monitored. This requirement that is especially valid for elements of a device that are most prone to incur damage or that are most likely to accumulate electrical charges during the process of creating a semiconductor device. As an example of an element that is most likely to be damaged by the occurrence of electrical charges of the type that have just been highlighted can be cited a layer of gate oxide that is typically created under the gate electrode of a Metal Oxide Silicon FET (MOSFET) since this layer is required to be very thin (about 100 Angstrom) for reasons of device performance requirements. The MOSFET device is typically interconnected to surrounding devices by creating metal interconnects to the gate structure and to the source/drain regions of the device. With the metal interconnect to the gate electrode in place, interconnects are established to the surface of the source/drain regions of the device. The metal interconnect to the gate electrode is prone to act as a collector of electric charges during the plasma etch that is required to create openings through an insulating layer of material in order to create the metal interconnects to the source/drain regions. The charge that accumulates on the gate electrode metal creates a high electrical potential between the gate electrode and the underlying silicon substrate, that is across the layer of gate oxide of the structure, raising the potential of damage to this layer of gate oxide, which is required to be very thin.
These and other negative effects of the accumulation of electrical charges during the creation of a semiconductor device must by understood and monitored. The invention provides such a method, which is simple to implement and cost effective to use.
U.S. Pat. No. 5,907,764 (Lowell et al.) shows a charge monitor and process.
U.S. Pat. No. 6,232,134 (Farber et al.) reveals a wafer charge monitoring method.
U.S. Pat. No. 6,060,329 (Kamata et al.), U.S. Pat. No. 5,861,634 (Hsu et al.) and U.S. Pat. No. 6,143,579 (Chang et al.) show related processes.